Technical Program Manager (Silicon Engineering)

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THE ROLE:

In this leadership role within the Engineering Core Team, the candidate will leverage their strong technical understanding of the end-to-end silicon engineering process, from SoC architecture and design through tape-out, post-silicon bring-up and production, to manage and drive the execution activities of cross-disciplinary engineering functions developing semi-custom ASIC solutions in collaboration with one of AMD’s largest customers.

The candidate will be part of the leadership team running the Chief Engineering Council (CEC) Forum, driving technical alignment, cross-functional execution, risk management, and timely decision-making across the program.

THE PERSON:

A self-driven, technically strong, execution-focused leader with excellent Program Management skills and a broad understanding of SoC architecture and design, Design Verification (DV), DFx/DFT, Physical Design (PD), packaging, firmware/software, post-silicon bring-up and productization.

The candidate should be comfortable engaging in technical discussions across engineering disciplines, understanding cross-domain dependencies and risks, challenging assumptions, and working with cross-functional teams, executive management, and customers to drive technically sound decisions and execution closure.

Must have strong communication, organizational, customer-facing, and influencing skills and be able to operate effectively in a fast-paced, geographically distributed, matrixed engineering organization.

Preferred experience level: 15+ years of SoC/ASIC engineering, technical program management, or technical leadership experience.

RESPONSIBILITIES:

1. Plan and drive end-to-end cross-functional technical execution of complex SoC/ASIC programs from architecture and requirements definition through design, verification, implementation, tape-out, post-silicon bring-up, qualification, and production.
2. Drive AMD product solution deliverables and alignment with customer platforms to ensure the highest level of customer satisfaction throughout the product lifecycle.
3. Engage with technical leadership to understand and document program scope, establish integrated schedules, identify critical technical dependencies, assess and manage program progress and risk, and create resource and budget plans.
4. Work closely with SoC Architecture, Design, IP, DV, DFx/DFT, PD, Packaging, Firmware/Software, Validation, Product Engineering, and Manufacturing teams to drive technical readiness and closure of cross-functional issues.
5. Develop a strong understanding of key program-level technical challenges and drive alignment on architecture, performance, power, area, timing, verification, testability, physical implementation, package, and silicon readiness trade-offs.
6. Partner with Chief Engineers, SoC Leads, Product Architects, and technical leads to identify cross-domain dependencies, drive root-cause analysis, assess technical and schedule impact, and facilitate timely engineering trade-off decisions.
7. Drive tape-out readiness and post-silicon readiness, ensuring critical Design, DV, DFx, PD, Packaging, Firmware, and Validation dependencies, risks, and closure criteria are understood and managed.
8. Drive cross-functional execution during post-silicon bring-up, debug, validation, qualification, and production readiness, ensuring critical silicon issues are appropriately prioritized and driven to closure.
9. Establish clear ownership and accountability for technical deliverables, proactively identify execution and technical risks, and drive mitigation/recovery plans to protect program milestones and customer commitments.
10. Represent the Semi-Custom Engineering organization in corporate, CEC, customer, and executive planning and execution forums.
11. Own clear executive-level program reporting covering technical readiness, schedule, critical-path items, risks, options, recommendations, and decisions required.
12. Work with the Finance team and engineering leads to maintain program resource and budget alignment.
13. Work with the Core Leadership Team, including Chief Engineer, BU Heads, SoC Leads, Product Architects, and relevant engineering teams, to ensure compliance with customer gate checklists and attainment of contractual milestones in partnership with Business Development.
14. Drive structured management of requirements and engineering changes, including assessment of impacts across architecture, design, DV, DFx, PD, package, firmware, silicon, schedule, and customer commitments.
15. Drive continuous improvement in engineering execution, program governance, technical readiness metrics, automation, and cross-functional processes.
16. Act as the “Voice of the Customer” while working with internal teams, balancing customer requirements with technical feasibility, quality, performance, power, area, cost, schedule, and business objectives.

REQUIRED SKILLS:

1. Strong technical foundation in SoC/ASIC design and development. This is a technical leadership role and requires significantly more than traditional program-management experience.
2. Strong understanding of the complete SoC development lifecycle, including architecture, RTL/design and IP integration, DV, DFx/DFT, synthesis, PD, timing and physical sign-off, packaging, tape-out, post-silicon bring-up, validation, qualification, and production.
3. Strong technical understanding of SoC architecture and design, including IP/subsystem integration, interfaces/interconnect, clock/reset architecture, power management, and overall SoC integration.
4. Good working knowledge of Design Verification, including verification planning, coverage, regression, bug management, and SoC-level verification readiness.
5. Good working knowledge of DFx/DFT, including scan, MBIST/BIST, manufacturing test, debug, and testability requirements.
6. Good working knowledge of Physical Design, including floorplanning, implementation, timing closure, power integrity, EM/IR, and physical sign-off.
7. Understanding of packaging and die/package interactions, including bump/interface planning, power delivery, signal integrity, thermal considerations, and package-level dependencies.
8. Understanding of post-silicon bring-up, silicon debug, validation, characterization, and product qualification, including interactions across silicon, firmware, package, platform, and system-level environments.
9. Demonstrated ability to understand complex cross-domain engineering issues, ask the right technical questions, challenge assumptions, identify dependencies and facilitate technically sound trade-off decisions.
10. Strong understanding of Performance, Power, and Area (PPA) trade-offs and their relationship to architecture, design, verification, physical implementation, packaging, cost, and schedule.
11. Excellent analytical, problem-solving, project planning, risk-management, and execution-management skills.
12. Proven ability to deliver large, technically complex, cross-functional silicon programs and strategic initiatives.
13. Ability to influence horizontally across multiple internal functional organizations and drive results and accountability without direct reporting authority.
14. Excellent written, verbal, presentation, and executive communication skills, with the ability to translate complex engineering issues into clear impact, options, trade-offs, recommendations, and decisions required.
15. Strong networking and interpersonal skills with demonstrated ability to work effectively with senior technical leaders, executives, customers, and partners.
16. Skilled in interfacing with customers and partners and managing complex joint-development projects.
17. Business savvy with the ability to think strategically and make intelligent technical-versus-business trade-off recommendations.
18. Ability to adapt to dynamic business, customer, and technical requirements and drive clarity and execution in ambiguous situations.
19. Energized by working in a fast-paced, matrixed technical organization and multi-site environment.
20. AI awareness and demonstrated use of AI and automation tools to improve engineering productivity, program execution, risk identification, communication, and decision support.

EDUCATION:

Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, or a related technical discipline.

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.

Compensation: Expected salary range: INR 7,000,630.00 per year to INR 10,000,900.00 per year