Silicon Power Architect, Reality Labs
Description
Reality Labs focuses on delivering Meta's vision through creating advanced AI-enabled wearables. The compute performance and power efficiency requirements of wearables require custom silicon. Reality Labs Silicon team is driving the state-of-the-art forward with breakthrough work in AI, augmented reality, computer vision, machine learning, graphics, displays, and sensors. Our chips will enable wearable devices where our real and virtual worlds will mix and match throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistors, through architecture, firmware, and algorithms. We are seeking a Silicon Power Architect to lead the development of next-generation silicon solutions for wearables. This role requires experience in low-power design techniques, power estimation, and convergence tool flows and management.
Responsibilities
Model and own use-case power for custom silicon by working closely with the systems team Influence the overall SOC IP's power requirements, including power states, high-level power tree, and power sequence requirements Work closely with architects of SOCs that optimize functions such as image compute and CPU/GPU workloads for our AR/VR products Work closely with PMIC and systems teams on the overall SOC power requirements Optimize the power architecture implementation to meet use case power goals Work across disciplines, brainstorm big ideas, build new methodologies, prioritize and coordinate multiple initiatives based on impact and deadlines, drive a concept into a prototype and ultimately guide the transition into a high-volume consumer product Understand the tradeoffs between general-purpose and custom compute mechanisms, be able to model data flows, and create detailed cost/benefit analysis Work on post silicon model to hardware correlation
Qualifications
Bachelor's degree in Computer Engineering or electrical engineering or a relevant technical field, or equivalent practical experience 6+ years of experience with production silicon including at least one product shipped Experience with methods for partitioning a solution across hardware and software, digital, and other multi-disciplinary boundaries in a system solution Experience in technology node scaling and projections Experience in custom IP block power estimates Experience of low power design principles across RTL, design and system level Experience in evaluating architectural trade-offs of performance, power, and area Experience employing scientific methods to debug, diagnose, and drive the resolution of cross-disciplinary system issues MSEE or PhD equivalent Experience in using AI agents for managing power tools and extracting results Experience in top down high-level-model to HW power modeling of system use cases Familiarity with high-level modeling tools like Synopsys Platform Architect or virtual prototyping tools is a plus Experience programming in C, C++, or Python Experience collaborating and/or leading in a team environment Experience working effectively as an individual and in a multidisciplinary team Experience solving ambiguous problems in a fast-changing consumer electronics field Results-oriented, self-motivated, proactive with demonstrated creative and critical thinking skills