Silicon Debug Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for engineers to help achieve that mission.

The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantages to Microsoft and enable our customers to achieve more.

As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Silicon Manufacturing and Product Engineering (SMPE) team is instrumental in defining and elivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.

We are looking for a Silicon Debug engineer to join the team to support our mission as a key role with driving silicon failure analysis, fault isolation, and product debug across Cobalt and Maia programmes.

#SCHIE #CSME #SMPE

The candidate will be expected to complete the following responsibilities: 

The Silicon Debug Engineer will own complex investigations from failure intake and reproduction through electrical fault isolation, physical-analysis hand-off, evidence-based disposition and root-cause closure. The engineer will collaborate across silicon, package, product, test, platform, manufacturing and supplier teams to improve product quality and debug efficiency. 

Specific responsibilities include:

• Lead FA/FI investigations covering first-silicon bring-up, manufacturing, reliability qualification, system integration and customer RMA failures. 
• Reproduce and characterize failures on ATE and system-level test environments using production and debug test programme, shmoo analysis, margin data and failure-signature correlation. 
• Isolate failures across memory, logic, interconnect, I/O, clock, reset, power and security subsystems using DFT diagnostics and electrical evidence. 
• Perform electrical failure analysis and fault localization using optical and laser-based techniques such as EMMI, LVI and LADA, where available. 
• Debug test hardware, load boards, sockets, test programme and test content; develop practical workarounds and corrective actions when the test solution contributes to a failure. 
• Analyze manufacturing and RMA data to identify silicon, package, test-coverage, setup or process issues and convert findings into actionable hypotheses. 
• Correlate ATE results with laboratory, OSAT, supplier and customer-platform behavior to validate silicon design, process, package and manufacturability against product specifications. 
• Define FA plans, select internal or third-party laboratory capabilities, prepare PFA requests and integrate EFA/PFA results into the final root-cause conclusion. 
• Drive cross-functional debug reviews, communicate technical evidence clearly and maintain traceable investigation records, decisions, risks and actions. 
• Develop and improve debug content, automation and data-analysis methods using Python and/or Java-based test environments. 
• Contribute to test-hole closure, screening improvements, escape prevention and lessons learned that scale across future custom-silicon programme. 
• Apply knowledge of platform, package, silicon power management and thermal behavior to resolve product-quality issues. 
• Support system-level test correlation and debug. 

Required Qualifications:

• Bachelor’s Degree in Electrical Engineering, Computer Engineering, Physics, Materials Science or a related technical field AND 3+ years of semiconductor product, test, failure-analysis or silicon-debug experience, OR equivalent experience. 
• 3+ years of hands-on experience in integrated-circuit failure analysis, fault isolation, silicon debug, ATE test engineering or test-programme/content development. 
• Experience debugging complex SoCs across at least two areas, such as boot, JTAG, clocks/resets, memory/MBIST, scan, high-speed I/O, power management, security or fuses. 
• Experience interpreting electrical test data and working across engineering teams to drive root-cause investigations to closure. 
• Experience debugging complex SoCs across at least two of the following: boot, JTAG, clocks/resets, memory/MBIST, scan, high-speed I/O, power management, security or fuse-related functions.  
• Experience interpreting electrical test data and partnering across design, DFT, product, package, manufacturing, platform or supplier teams to drive root-cause closure.  

Preferred Qualifications:

• Experience with HPC/AI/CPU/GPU or advanced SoC silicon.
• Hands-on experience with ATE, V93000/Smartest 8, test hardware/debug and system correlation.
• Experience in FA/FI and EFA/PFA techniques, such as EMMI, LVI, LADA, X-ray, C-SAM, FIB or SEM.
• Knowledge of DFT/DFM, scan, MBIST/BISR, device physics and semiconductor/package failure modes.
• Experience with first-silicon bring-up, NPI, reliability, RMA and test-hole closure.
• Python/Java and statistical analysis skills for debug automation, data analysis and DOE.
• Strong communication, judgement and cross-functional collaboration skills.

Screening Requirements

• Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
• This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations.  As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.

This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.