Silicon Architect, Subsystem Architecture

Description

Reality Labs focuses on delivering Meta's vision through creating advanced AR/AI enabled wearables. The compute performance and power efficiency requirements of wearables require custom silicon. Reality Labs Silicon team is driving the state-of-the-art forward with breakthrough work in AI, augmented reality, computer vision, machine learning, graphics, displays, and sensors. Our chips will enable wearable devices where our real and virtual worlds will mix and match throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistors, through architecture, firmware, and algorithms. As a Memory Architect on the Subsystem Architecture team, you will work with senior memory architects to analyze and define on-chip memory for the accelerator subsystems and IPs in our wearable chips, from caches and scratchpads down to SRAM selection, balancing power, performance and area (PPA) under tight wearable budgets.

Responsibilities

Analyze memory requirements per workload across accelerator subsystems, including caches, scratchpads and DSP local memories Evaluate SRAM options (compiled or custom, bitcell, banking, low-voltage and retention modes) and recommend the best fit for each memory Build memory models and power, performance and area comparisons to inform architecture decisions Support studies on memory hierarchy trade-offs, such as cache sizing and on-chip versus off-chip memory, eventually owning end-to-end analysis and next-generation memory system architecture for one or more subsystems Track emerging memory technologies (such as MRAM, RRAM, eDRAM, 3D-stacked memory and compute-in-memory) and assess their fit for wearable subsystems Correlate memory estimates with pre-silicon and silicon data, and inform improvements to modeling methodologies Work with senior memory architects, IP and DSP architects, memory and circuit design teams, and software and firmware teams across multiple programs

Qualifications

Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta 2+ years of experience in silicon architecture, memory design, or related silicon engineering disciplines Experience, through industry, internships or graduate research, in at least one of: memory hierarchy and cache analysis, or SRAM circuit design Understanding of how memory technologies, architectures and microarchitectures (for example SRAM bitcell, Vmin, leakage and banking) affect the power, performance and area of memory-intensive systems Experience building analytical, functional and cycle-accurate models to evaluate memory trade-offs Publications at venues such as ISCA, MICRO, HPCA, ISSCC or VLSI Symposium Experience with SPICE, memory compilers or low-voltage SRAM Experience sizing caches, scratchpads or DSP memories for accelerator workloads Research or industry experience with emerging memory technologies PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field, with research in memory systems or memory circuits Experience in both memory hierarchy and cache analysis and SRAM circuit design

Compensation: $114,000/year to $172,000/year + bonus + equity + benefits