Signal Integrity Architect
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Description and Requirements
Job Responsibilities：
1. Lead next-generation signal integrity architecture from technology concept through product delivery and mass production.
2. Define end-to-end interconnect architectures for board, chassis, tray, cable, and rack-scale copper or optical interconnects. General-purpose x86/ARM servers, storage, and network systems
3. DDR5/DDR6, MRDIMM, SOCAMM/CAMM, and other high-bandwidth memory interfaces
4. PCIe/CXL, 112G/224G Ethernet, InfiniBand, UCIe, and other emerging high-speed interfaces
5. Own end-to-end channel budgets and electrical requirements, including insertion loss, return loss, crosstalk, impedance, skew, jitter, eye margin, COM, BER, and protocol compliance.
6. Develop SI architecture specifications, channel topologies, routing constraints, stackup requirements, interface control documents, and design sign-off criteria.
7.Drive package-board-system co-design, including BGA breakout, via transitions, backdrilling, connectors, sockets, cables, retimers and optical-electrical boundaries.
8. Define reusable S-parameter, connector, cable, SerDes, and behavioral-model requirements; ensure model accuracy, causality, passivity, correlation.
9. Lead complex SI debug and root-cause analysis across package, PCB, connector, cable, clocking, power noise and link-training behavior.
10. Quantify manufacturing variation, tolerance, aging, temperature, and supplier effects; define robust design margins, yield targets, and production screening requirements.
11. Partner with PI, package, board, mechanical, thermal, power, firmware, validation, manufacturing, and system architecture teams to optimize complete platform performance.
12. Lead architecture and design reviews and provide technical guidance through concept, schematic, layout, EVT, DVT, PVT, qualification, and mass production
Job Requirements：
1. Master’s or Ph.D. degree in Electrical Engineering, Electromagnetics, Applied Physics, or a related field.
2. 10+ years of signal integrity, high-speed digital design, server, networking, storage, or data center system development experience.
3. Strong foundation in electromagnetic fields, transmission-line theory, S-parameters, high-speed I/O signaling, jitter, crosstalk, equalization, and channel-margin analysis.
4. Proven experience defining and signing off high-speed links across PCB, connectors, cables, and complete systems using circuit and electromagnetic simulation.
5. Strong knowledge of PCIe/CXL, Ethernet, DDR memory interfaces, SerDes architecture, clocking, and relevant electrical compliance methodologies.
6. Hands-on experience with TDR, VNA, high-bandwidth oscilloscopes, BERTs, probing, fixture de-embedding, correlation, and hardware root-cause analysis.
7. Hyperscale/cloud data center, high-density server, switch, storage, or rack-scale system experience.
8. Experience with advanced package and chiplet technologies, including 2.5D/3D integration, package-board co-design.
9. Experience with PCIe Gen6/Gen7, CXL 3.x, 112G/224G Ethernet, retimers, and co-packaged or pluggable optics.
10. Experience with DDR5/DDR6, MRDIMM, SOCAMM/CAMM, memory-channel topology, and power-aware timing analysis.
11. Expertise in IBIS/IBIS-AMI, S-parameter processing, passivity/causality enforcement, SPICE, statistical link analysis, and channel-compliance metrics.
12. Proficiency with industry SI/EM tools such as Ansys HFSS/SIwave, Cadence Clarity/Sigrity, Keysight ADS, CST, HSPICE, or equivalent platforms.
13. Experience automating SI workflows and design-space exploration using Python, MATLAB.
14. Direct technical engagement with CPU/SerDes vendors, global Tier 1 PCB manufacturers, connector, cable, optics, and test-equipment suppliers.
15. Strong technical leadership, cross-functional influence, written communication, and executive/customer presentation skills.