Principal Verification Engineer

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Job Description:

Microchip’s Communications Business Unit (CBU) develops high-performance networking, connectivity, and edge compute semiconductor solutions that power communications infrastructure, data centers, automotive systems, aerospace and defense platforms, and industrial applications. Our global team works across the full product lifecycle to deliver innovative products that enable the world’s most demanding connected systems. 

The CBU Product Development team is engaged throughout the device R&D cycle, from concept and design through implementation. Once a prototype is available, we support embedded software development and system-validation lab testing through mass-market production release. Our experienced chip-development team uses the latest semiconductor tools and methodologies, together with advanced process technologies, to develop state-of-the-art networking devices.

As a Principal Engineer on the CBU Product Development team, you will be responsible for verifying digital integrated circuits at the block or device level. You will collaborate with chip architects, subsystem leads, and verification team members to deliver increasingly complex designs in a friendly, professional environment.

The role of the Principal Engineer includes: 

• Verification

  • Own the verification of complex digital integrated circuits at the block, subsystem, or device level.
  • Understand the device requirements and functional description to ensure compliance with specifications and error-free operation.
  • Plan verification activities, develop testbenches, and execute tests.
  • Develop verification platforms using the UVM methodology and SystemVerilog.

• Technical Leadership

  • Deliver verified designs at the Device, Subsystem or Block level
  • Partner with a dedicated Design Lead to deliver high-confidence designs
  • Verify designs implemented in SystemVerilog RTL using industry-standard methodologies.

• Domain Expertise

  • Contribute to the development and enhancement of verification technologies and methodologies.

  • Cross Functional Responsibility

  • Collaborate with Software and Validation teams to deliver devices that integrate into a wider system.
  • Participate in Product Validation during the prototype stage of development.

Requirements/Qualifications:

• Bachelor’s or Master’s Degree in Electrical Engineering or Computer Engineering
• 8+ years related experience
• Excellent analytical and debugging skills and the ability to proactively solve issues
• Proven ability to thrive on, learn and adapt to new methodologies and technologies
• Strong coding skills
• Experience using one or more of System Verilog/Verilog/VHDL, Tcl/Perl/Python, C/C++
• Excellent verbal and written communication skills in English
• Experience with verification methodologies, including UVM, formal verification, and constrained-random verification.

Travel Time:

0% - 25%

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