Physical Design & Signoff CAD Engineer
Description
Meta's Silicon Engineering team is building custom silicon infrastructure to power the next generation of AI and data center workloads at scale. The Infra Silicon Physical Design CAD team develops and scales the RTL-to-GDSII implementation and signoff flows that our designers use to tape out large, high-performance SoCs on leading-edge process nodes. As an ASIC Engineer for a Physical Design & Signoff CAD Engineer you will own and advance our implementation and signoff methodology from synthesis, place and route, and PPA optimization through timing, physical, and reliability signoff; to build the infrastructure and AI-assisted automation that makes these flows fast, reproducible, and scalable across many designs and teams.
Responsibilities
Develop, deploy, and maintain the end-to-end RTL-to-GDSII physical design implementation flow, including synthesis, floorplanning, placement, CTS, routing, and PPA optimization Own and improve signoff methodology across static timing analysis, electromigration and IR drop analysis, physical verification, power analysis, logic equivalence checking, and SDC/UPF quality checks Support active tapeout programs on leading-edge process nodes, partnering with physical design, STA, and design teams to debug flow and signoff issues and drive them to closure Build and extend CAD infrastructure: flow execution harnesses, run-tracking and QoR dashboards, and design release / version control systems Develop scalable, AI-assisted tooling to automate flow setup, triage, QoR analysis, and optimization decisions Qualify new tool versions, technology collateral, and reference methodologies from EDA vendors and foundry partners Document methodology and enable designers through training, office hours, and support Collaborate with CAD, physical design, and silicon partner teams across multiple sites and time zones
Qualifications
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience 2+ years of experience in physical design implementation and/or CAD methodology development Working knowledge of the overall RTL-to-GDSII physical design flow Hands-on experience with implementation flows including synthesis, place and route, and PPA optimization Experience with signoff flows in one or more of: static timing analysis, electromigration and IR drop analysis, physical verification, power analysis, logic equivalence checking, SDC quality checks, UPF quality checks Scripting and automation experience (e.g., Tcl, Python) applied to EDA flows Experience collaborating with design teams and debugging flow issues through to resolution Hands-on tapeout experience on leading-edge process nodes 3+ years of combined physical design implementation and CAD experience Experience building CAD infrastructure: flow execution harnesses, QoR/run dashboards, design release and version control systems Experience developing scalable systems that apply AI/ML to EDA or engineering workflows Experience working directly with EDA vendors and foundry partners on tool and collateral qualification Breadth across both implementation and signoff rather than a single stage Experience supporting large, multi-site SoC programs