Physical Design Engineer

Summary

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.

Description

APPLE INC has the following available in Austin, Texas. Work on graphics projects from start to end for clock implementation which involve multiple clock domains. Work on clock architecture and designing high speed clock distribution circuits; Responsible for clock planning, building simulation models (Using Spice), & interacting with Floorplan owner to understand any Power domain/routing/placement challenges for the clocking. Involve in Clock repeater studies for a certain process technology with different size buffer, fanout, metal spec studies were done (Using Spice) and tabulated in excel for implementation engineer to choose right cell and layer based on nature of clock; and Involving in Clock cell definition and sizes and family of custom clock cell needed for a particular process technology. 40 hours/week.

Minimum Qualifications

• Master’s degree or foreign equivalent in Electrical and Computer Engineering or related field and 1 year of experience in the job offered or related occupation.
• 1 year of experience with each of the following skills is required:
• Build high-speed clock distribution networks optimized for performance and reliability
• Implement designs across multiple clock domains with proper synchronization and isolation
• Execute clock planning with considerations for power domains, routing congestion, and placement constraints
• Optimize clock trees to minimize latency and skew for high-performance designs
• Analyze and select clock repeater and buffer configurations across various process technologies
• Tune metal layer usage and fanout strategies to enhance clock signal integrity and timing
• Debug physical design verification (PDV) issues such as DRC, LVS, shorts, and opens during clock construction

Preferred Qualifications

• N/A