Packaging Engineer

Summary

Looking for a senior level IC packaging engineer to develop exciting new products. You will be responsible providing Custom Silicon packaging solutions in a module/system for various consumer markets.

Description

• In this fast-paced environment, your role is to interface between internal product/device design, quality, supply chain, and the external suppliers to develop and deploy new packaging technologies.

• Must be a good negotiator and influencer to drive industry to meet company needs.
• We are looking for individuals who are very innovative with a proven track record to reduce package development cycle and qualify devices into a high-volume manufacturing environment.

  Responsibilities

  • Define new package characteristics based on unique module and system level performance, cost, and footprint requirements.
  • Define package/packaging specifications.
  • Work with external suppliers on package design, new material, new equipment selection and process flow development.
  • Perform initial proof of concept sample build, POR establishment, package and process qualification, reliability test, yield analysis and enhancement.
  • Coordinate with other packaging and cross-functional team members to comply with product development/ramp schedule.
  • Deliver package/packaging milestones on time.
  • Define packaging roadmap based on long term packaged product requirements.
  • Work closely and Manage suppliers’ R&D activities.

  Minimum Qualifications

  • BS and 10+ years of relevant industry experience.

  Preferred Qualifications

  • M.S or Ph.D. degree in mechanical engineering, physics, materials science or similar disciplines with a minimum of 10 years of experience in IC packaging. AutoCAD, APD and multi-physics simulation knowledge is a plus.
  • Industry experience and work on WLP either in IDM or Fabless companies.
  • Knowledge and hands-on experience on Wafer Bumping and Dielectric materials and their pros/cons is a must.
  • Some hands-on knowledge in Manufacturing assembly processes; such as wafer back-grind, wafer dicing, Flip Chip die attach, encapsulation/molding, under-fill, ball attach, package singulation and Tape & Reel.
  • In-depth knowledge in Wafer Level Chip Scale Packaging (RDL/Wafer Bumping & BEOL Assembly processes for Fan-In & Fan-Out designs).
  • Good knowledge on Package Qualification and Reliability testing.
  • Expert level knowledge of common reliability failure modes. Able to understand device physics and component/board level reliability testing.
  • Proven track record to bring a product/package from conceptual stage to development and to HVM environment.
  • Ability to construct Designs of Experiments and down-select materials and processes.
  • Good written and verbal communication skills. Able to present ideas, design concepts, data and plan with high confidence at team meetings and executive review meetings.
  • Able to perform independent research and development work with minimal supervision.