Master Thesis: Learned Evidence Ranking for ASIC Verification Quality and Debug using AI ML

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“Learned Evidence Ranking for Failure Diagnosis and Automated Testbench Quality Assessment in UVM-Based ASIC Verification”

A modern ASIC verification testbench executes hundreds of thousands of events per test: scoreboard comparisons, randomized stimulus generation, protocol transactions, configuration-database accesses and synchronization between testbench components. Only a small fraction of these events is printed, because a message exists only where a verification engineer has chosen to add one.

A single regression test in our environment can produce an 11 MB log containing HDL warnings, UVM informational messages, and SystemC messages and warnings. At the same time, it performs many scoreboard comparisons, randomizations and configuration-database accesses that produce no output. When a test fails, an engineer must manually locate the handful of events that determine the root cause. This can take several hours per failure; one case study measured close to 3.5 hours across seven manual steps. The decisive evidence consisted of one error message, 25 repeated warnings and one buffer-size value—approximately 500 bytes of useful information in an 11 MB log.

Two developments make automation tractable. First, the accelerator testbench is being restructured so that its messages are machine-readable. The UVM report server is the central point through which all verification messages flow, and a drop-in replacement emits JSONL alongside the human-readable log. Each event is tagged with its component type, hierarchy, simulation phase and causal context, without requiring changes to the existing testbench code. Second, several resolved trouble reports document the evidence that led to each root cause, providing a basis for supervised training.

The subject of this thesis is total observability: capturing what the testbench does rather than only what it reports. Scoreboard comparisons, configuration accesses, TLM transactions and randomization outcomes will be captured through UVM callbacks and factory overrides. The level of capture will range from lightweight, always-on monitoring in nightly regression runs to deep tracing for targeted debugging.

What you will do

• Develop a data-driven framework for automated failure diagnosis and testbench quality assessment in UVM-based verification.
• Develop a portable instrumented observer layer with measured overhead.
• Capture execution events, scoreboard comparisons, randomization outcomes, transaction flows and configuration accesses beyond conventional UVM messaging.
• Develop a multi-dimensional correlation engine using temporal, structural, semantic and historical information.
• Train the relevance model against evidence extracted from resolved trouble reports.
• Rank captured events by diagnostic relevance when a failure occurs, helping replace manual log inspection.
• Evaluate the model against engineer-identified evidence and manual triage effort using production regression data from an Ericsson accelerator IP.
• Use an existing fine-tuned LLM for end-to-end diagnosis evaluation.
• Develop a quality-assessment prototype that produces an auditable testbench readiness score from empirically weighted structural, behavioral and effectiveness checks.
• Investigate which correlation dimensions carry the most predictive weight and whether this varies by failure class.
• As a stretch goal, explore whether pre-failure patterns, such as drift in scoreboard pass rates, can be detected before an error message appears. You may also investigate whether test quality can be predicted from configuration before simulation starts.

The skills you bring

• Master´s student in electrical or computer engineering, computer science, embedded systems, or a similar field.
• Knowledge of computer architecture, ASIC design and RTL/HDL coding.
• Experience with SystemVerilog and testbench design; working knowledge of UVM is preferred.
• Scripting experience, preferably Tcl or Python, for EDA tools.
• Fundamentals of artificial intelligence and machine learning.
• Exposure to at least one AI/ML model architecture, from data preparation through evaluation.
• An analytical and research-oriented mindset.
• Interest in verification, observability and data-driven engineering.

Why join Ericsson?

At Ericsson, you´ll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what´s possible. To build solutions never seen before to some of the world’s toughest problems. You´ll be challenged, but you won’t be alone. You´ll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next.
 
What happens once you apply?

Click Here to find all you need to know about what our typical hiring process looks like.Encouraging a diverse and inclusive organization is core to our values at Ericsson, that's why we champion it in everything we do. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity Employer. learn more.

Primary country and city: Sweden (SE) || Stockholm

Req ID: 791543