Leader, ASIC Engineering | RTL, Datapath, Network Processing Unit

Cisco•Published 14 hours ago•First seen 7 hours ago

Meet the Team
Come join us and be part of the Cisco SiliconOne team and take part in crafting Cisco's groundbreaking Enterprise and Service Provider solutions by crafting some of the most complex chips being developed in the industry with the opportunity to get full exposure to all aspects of the systems and applications we build (Silicon, Hardware, Software, telemetry, security, etc). Our group offers a rare combination of a startup culture with the benefits of working for the top tier networking company in the world!

Your Impact
Cisco SiliconOne team is looking for an expert and talented ASIC Engineering Leader. You will have an ASIC design background with hands-on experience in RTL design with in-depth knowledge of ASIC/SoC development cycle, the best industry practices, from specification through tape-out and lab validation, and a proven track record of success in high-performance/high-volume products.

Leads ASIC engineering teams to deliver high-performance, power-efficient, and reliable ASICs for Cisco's diverse product platforms.
Leads teams in defining, designing, and verifying ASICs and ASIC subsystems to ensure alignment with stringent power, performance, and area (PPA) goals for deployment across Cisco’s platforms.
Drives collaboration cross-functionally to achieve high-volume production with uncompromised quality.
Defines processes, methodologies, and tools for the design and implementation of complex ASIC developments, ensuring scalability, efficiency, and innovation.
Oversees the documentation, development, and validation of ASIC subsystems, ensuring robust designs that meet the demanding requirements of Cisco's product ecosystem.
Drives all aspects of implementation: Specification, design, timing-analysis, power-optimization, flow automation, optimization of the logic for low power and area; highlighting issues and standard methodologies for power and area optimization.
Review complex designs and makes recommendations for improvements.
Act as the design leader, owning and leading all the above aspects, including driving the technical decisions made at the program level with rest of the design teams, conducting weekly design meetings, sync-ups with stake holders and cross functional teams like Architecture, DV, PD, Emulation, SW, PSV and Silicon Operations.
Drives design solutions across the business. Ensure culture of code reviews and postmortems.

Minimum Qualifications

BS/MS and 15+/13+ years respectively of hands-on experience in large-scale, high-performance ASIC.
Have led a design team for a minimum of 4 years
Architecture and implementation specification creation.
RTL development (Verilog, System Verilog, VCS, Spyglass, CDC, Formal verification)
Experienced in system debug and SW/HW bring-up, system validation of silicon towards FCS.
Gate-level understanding of RTL and Synthesis
Good written/verbal interpersonal skills and leadership skills.

Preferred Qualifications

Worked in design and execution management of high-scale, high-performance ASICs.
Planning overall design execution strategy and defining the requirements.
Conducting & leading various architecture reviews.
Driving complex debugs and system level integration aspects
Valid experience in implementation: specification, RTL design, lint, cdc, timing analysis, formal verification, system testing.
Mentoring the senior resources in the team on architectural and design strategies.
Good interpersonal skills, and validated leadership to accurately describe issues/improvements and lead team for on-time completion.
Excellent communication skills both verbal and written

Why Cisco?

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you.

Disclaimer

To ensure that we hire the best talent in the right way, we follow a strict hiring process and recently, Cisco has been made aware of fraudulent recruiters claiming to be from the company. Please be advised that any communication from Cisco about careers will:

be in direct response to an application you have submitted through the company career site
begin with screening or an interview
originate from a Cisco email address, and
be conducted across email, phone, or WebEx

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If you are the target of a recruiting scam, consider filing a report with your local law enforcement authorities. Cisco bears no responsibility, and cannot be held liable, for any claims, damages, expenses, or other inconvenience resulting from or in any way connected to recruiting scams.

Leads ASIC engineering teams to deliver high-performance, power-efficient, and reliable ASICs for Cisco's diverse product platforms.

Leads teams in defining, designing, and verifying ASICs and ASIC subsystems to ensure alignment with stringent power, performance, and area (PPA) goals for deployment across Cisco’s platforms.

Drives collaboration cross-functionally to achieve high-volume production with uncompromised quality.

Defines processes, methodologies, and tools for the design and implementation of complex ASIC developments, ensuring scalability, efficiency, and innovation.

Oversees the documentation, development, and validation of ASIC subsystems, ensuring robust designs that meet the demanding requirements of Cisco's product ecosystem.

Drives all aspects of implementation: Specification, design, timing-analysis, power-optimization, flow automation, optimization of the logic for low power and area; highlighting issues and standard methodologies for power and area optimization.

Review complex designs and makes recommendations for improvements.

Drives design solutions across the business. Ensure culture of code reviews and postmortems.

Minimum Qualifications

BS/MS and 15+/13+ years respectively of hands-on experience in large-scale, high-performance ASIC.

Have led a design team for a minimum of 4 years

Architecture and implementation specification creation.

RTL development (Verilog, System Verilog, VCS, Spyglass, CDC, Formal verification)

Experienced in system debug and SW/HW bring-up, system validation of silicon towards FCS.

Gate-level understanding of RTL and Synthesis

Good written/verbal interpersonal skills and leadership skills.

Preferred Qualifications

Worked in design and execution management of high-scale, high-performance ASICs.

Planning overall design execution strategy and defining the requirements.

Conducting & leading various architecture reviews.

Driving complex debugs and system level integration aspects

Valid experience in implementation: specification, RTL design, lint, cdc, timing analysis, formal verification, system testing.

Mentoring the senior resources in the team on architectural and design strategies.

Good interpersonal skills, and validated leadership to accurately describe issues/improvements and lead team for on-time completion.

Excellent communication skills both verbal and written

Why Cisco?