Intern AFG Memoire
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.
Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace, industrial and health.
We are looking for a final-year engineering or Master’s student, or pursuing an equivalent qualification, in microelectronics, electronics, computer engineering, computer science, applied physics, data science, or a related discipline
Title: Intern
Location: Sophia-Antipolis, France
Duration: 6 months
From: early Q1 2027
We are considering three possible internship topics and expect to select for only one of them. When applying, please indicate the topic that best matches your interests and experience. You may also mention if you would be interested in extended topic.
Internship 1: Advanced SRAM Design and Self-Timing Optimization
Internship 2: Statistical Yield Optimization for Next-Generation SRAM Memories
Internship 3: Power Characterization Methodology for Memory Compilers
What Matters Most
Curiosity, enthusiasm, and a desire to learn. Whether your background is in software, electronics, data science, AI, or another engineering field, we encourage you to apply.
This is an opportunity to gain hands-on experience in SRAM development and contribute to real-world projects spanning memory design, characterization, validation, and compiler implementation.
Internship 1 : Advanced SRAM Design and Self-Timing Optimization
Investigate and optimize SRAM self-timing architectures to improve frequency and robustness for advanced technology nodes, through enhanced bitcell tracking methodologies and adaptive timing path design.
About the Internship
- Advanced embedded SRAMs must maintain both robustness and performance across increasingly challenging manufacturing process variations. One key aspect is the design of self-timing mechanisms that accurately track the behavior of memory bitcells under extreme process conditions.
- Current solutions combine bitcell tracking and logic-based timing paths, but opportunities exist to improve correlation with worst-case memory behavior while minimizing performance penalties.
What You Will Do·
- Analyze the impact of advanced process variations on SRAM self-timing paths.
- Study and benchmark different timing tracking methodologies.
- Investigate bitcell-based and hybrid tracking architectures.
- Develop simulation and evaluation methodologies.
- Propose and validate architectural improvements to improve performance while preserving robustness.
Relevant knowledge and interests
We are interested in your foundational knowledge, curiosity, problem-solving approach and willingness to learn. You don’t need experience in every area listed below.
- Microelectronics, CMOS circuit design, and SRAM architecture
- VLSI design, advanced technologies
- Circuit simulation and variability analysis
- Methodical mindset and good presentation skills
Expected outcomes
- The internship will provide hands-on exposure to industrial memory IP development and advanced-node design challenges, with the opportunity to contribute to methodologies used in next-generation embedded memory products.
- We believe this topic would be an excellent opportunity for a curious student seeking experience in advanced integrated circuit design within a leading EDA and IP company.
Internship 2 : Statistical Yield Optimization for Next-Generation SRAM Memories
Develop novel variation-aware methodologies to optimize SRAM robustness and yield under statistical process variations, while minimizing the impact on Performance, Power, and Area (PPA).
About the Internship
- SRAM memories are a critical component of modern AI and high-performance computing systems. As technology scaling increases device variability, achieving extremely high yield targets requires advanced statistical design methodologies that go beyond conventional margin-based approaches. Optimally balancing robustness across bitcells, sense amplifiers, and peripheral circuits has become a major challenge for next-generation SRAM products.
What You Will Do
- Analyze the impact of statistical process variations on SRAM yield and robustness.
- Investigate yield allocation strategies across SRAM building blocks.
- Develop variation-aware design and optimization methodologies.
- Evaluate yield versus PPA trade-offs using advanced statistical analysis techniques.
- Propose and validate methodologies to improve overall SRAM robustness.
Relevant knowledge and interests
We are interested in your foundational knowledge, curiosity, problem-solving approach and willingness to learn. You don’t need experience in every area listed below.
- Microelectronics, CMOS circuit design and SRAM architecture
- Circuit simulation and interest in statistical analysis
- EDA methodology and tools enhancement
- Logical reasoning and methodical approach to problem solving
Expected Outcomes
- The internship will provide hands-on exposure to advanced SRAM design methodologies, high-sigma statistical analysis, and yield optimization techniques used in state-of-the-art memory IP development. The student will contribute to innovative robustness methodologies for future AI and high-performance computing products.
Internship 3 : Power Characterization Methodology for Memory Compilers
Investigate and optimize power characterization methodologies for SRAM memory compilers to improve the accuracy of power models while limiting characterization time and simulation cost.You will explore stimuli definition, circuit simulation, characterization and interpolation strategies, and validation of power trends across different memory architectures, instance sizes, and design features.
About the Internship
- Power consumption is a key competitive factor for embedded memory products. Providing accurate power models is essential to enable reliable power estimation and optimization during System-on-Chip design.
- Memory compilers can generate a large number of instances covering different memory sizes, architectures, configurations, and design features. An optimized characterization and interpolation strategy is therefore required to minimize the number of electrical simulations while maintaining accurate and consistent power models across the entire compiler solution space.
- The generated power information is delivered through Liberty models and must exhibit physically consistent trends based on instance dimensions, memory architecture, operating mode, and enabled features.
What You Will Do
- Understand memory compiler architectures and the different memory power modes.
- Review power stimuli, critical signals, initialization sequences and simulation settings.
- Optimize instance selection and interpolation to reduce simulation effort.
- Validate Liberty power trends across instance sizes, configurations and features.
- Apply the methodology to different compilers, such as single-port, dual-port and ROM.
Relevant knowledge and interests
We are interested in your foundational knowledge, curiosity, problem-solving approach and willingness to learn. You don’t need experience in every area listed below.
- Microelectronics, CMOS circuit design, and SRAM architecture
- Circuit simulation and power analysis
- Data analysis and scripting, preferably Python, Tcl or Shell
- Analytical skills and interest in EDA methodologies
Expected Outcomes·
- The internship will provide hands-on exposure to industrial memory IP development, transistor-level power analysis, electrical characterization flows, and the modeling methodologies used to support power estimation during System-on-Chip design.