Design Verification Engineer

Summary

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.

Description

APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Ensure bug-free first silicon for part of the SoC / IP and developing detailed test and coverage plans based on the micro-architecture. Develop verification methodology suitable for the IP, ensuring a scalable and portable environment. Develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage. Develop verification plans for all features under care, execute verification plans, including design bring-up, DV environment bring- up, regression enabling all features under my care, and debug of the test failures. Develop block, IP and SoC level test-benches track and report DV progress using a variety of metrics, including bugs and coverage. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $174,149 - $225,300/yr and your base pay will depend on your skills, qualifications, experience, and location.

PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html.
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Minimum Qualifications

• Master’s degree or foreign equivalent in Electrical Engineering, Electronics Engineering or a related field.
• Experience and/or education must include:
• Utilizing System Verilog for constrained random verification and functional coverage.
• Utilizing UVM to develop verification environments and implement directed and random test cases.
• Utilizing C and C++ demonstrating strong software skills in data structures and algorithms
• Utilizing Python and Perl for test vector generation and executable scripts.
• Utilizing EDA tools for testbench simulations, debugging, and coverage closure.
• Utilizing High-speed interface protocols for verifying high bandwidth, low power data communication systems.
• Utilizing Digital Design for understanding ASIC design flows and verification.
• Utilizing Computer Architecture for exploration of memory subsystem and architecture trade-off analysis.

Preferred Qualifications

• N/A

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant