Design Verification

Summary

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Description

APPLE INC has the following available in austin, Texas. Create software to verify architecture and functionality of pre-silicon hardware designs. Program in object-oriented programming, C, C++, System Verilog, Python, and Perl. Run regressions, performing bug tracking, and analyzing code and functional coverage. Simulate and debug Register Transfer Level (RTL). Collaborate with all fields (vertical product model). Ensure the quality of the SOC or an IP or subsystem. Review design and architecture specifications and working closely with design and micro-architecture teams. Developing test plans, tests and coverage plans as well as define the next generation verification methodology & testbenches. Collaborate with design, architecture and software to understand the use cases and corner conditions and drive test cases. Work on one or several of the following types of IP:- Neural Engine hardware - DRAM subsystem, memory controller logic - Encode and Decode systems for ProRes and other codec formats such as VP9, AV1- Hardware security, including cryptographic algorithm implementations - High-Speed 10 standards such as PCI Express, DisplayPort, MIPI- Power management and fabric infrastructure - Memory cache management - Display Subsystem - Debug Subsystem for variety of panels and products. 40 hours/week.

Minimum Qualifications

• Master's Degree or foreign equivalent in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering, or related field and 5 years of experience in the job offered or related occupation.
• Education and/or experience must include:
• Utilizing Computer Architecture knowledge to understand micro-architecture of various design blocks.
• Utilizing System Verilog/UVM to develop test-bench code and test-sequences for verifying the design blocks.
• Using Python or Perl for scripting to create design verification collaterals.
• Using NCSIM and Xcelium for waveform debug to understand and triage regression failures.
• Utilizing assertions writing to verify RTL for corner-case scenarios.
• Implementing Digital Design knowledge to understand design architecture of subsystem.
• Utilizing functional coverage and code coverage understanding to test coverage holes in design verification of IP blocks.

Preferred Qualifications

• N/A

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