ASIC Engineer, Formal Verification

Description

Meta is hiring ASIC Formal Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Formal Verification to build IP and System On Chip (SoC) for data center applications. As a Formal Verification Engineer, you will be part of a team working with experienced engineers across the industry, focused on developing innovative ASIC solutions for Facebook’s data center applications. You will be developing comprehensive formal testplans and be responsible for complete formal verification sign-off of single or multiple complex blocks. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success.

Responsibilities

Propose, implement and promote the Formal Verification Methodology to be used across the group, both at the top level and at the block level Work with Architecture and Design teams to come up with Formal Verification specification and implementation Define Formal Verification scope, create Formal environment and close coverage with targeted Formal Verification Techniques at IP, Subsystem and SoC level Build reusable/scalable environments for Formal Verification and deploying tools Evaluate and recommend EDA solutions for Formal Verification

Qualifications

Bachelor's degree in Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience 2+ years of experience in formal verification Experience with Formal Verification applications including datapath, sequential equivalence, Xprop, Clock Gating, connectivity etc Experience with formal verification methodologies, complexity reduction techniques, and abstraction techniques Experience partnering with architecture, design, and validation teams to define formal verification scope and drive sign-off Fluency in hardware description languages, such as SystemVerilog and SVA Proficiency in scripting languages such as Python, Perl, or Tcl Experience with JasperGold or VC-Formal Experience in formal property verification of complex compute blocks like DSP, CPU, GPU or HW accelerators Experience with simulators and waveform debugging tools Experience interpreting hardware specifications and extracting design behaviors and properties for formal verification Experience with complex SoCs Experience with development of fully automated flows from specification to fully verified designs Formal verification experience in clock domain crossing, IP-XACT based register verification and low power