Senior Silicon Design Verification Engineer

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next-generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will be part of a high-impact Research and Development team creating cutting-edge hardware and software solutions that enable Google's continuous innovations in mobile image and AI processing. Your responsibilities will extend beyond standard verification closure, lead testbench architecture, build reusable Universal Verification Methodology (UVM) verification components, drive end-to-end system testing, and establish best Design Verification (DV) practices across the organization.The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first-party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.

Responsibilities

• Plan the verification of complex digital design blocks by thoroughly understanding architectural specifications and collaborating closely with Design/Architecture teams to map out critical verification scenarios and edge cases.
• Architect, implement, and enhance scalable constrained-random verification environments using SystemVerilog and UVM, or execute formal verification strategies using SystemVerilog Assertions (SVA) and industry-leading formal tools.
• Drive root-cause debugging of failed tests alongside RTL Design Engineers to ensure functional correctness and high reliability prior to tape-out.
• Define and manage functional and code coverage models, drive coverage closure workflows, and identify architectural holes to ensure tape-out readiness.
• Lead verification sub-initiatives across block and system levels while mentoring junior DV engineers to support team execution.
  

Minimum qualifications:

• Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience.
• 8 years of experience in silicon digital design implementation or verification.
• Experience verifying digital logic at RTL using SystemVerilog for ASICs.
• Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems).
• Experience with object-oriented programming.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering or Computer Science.
• Experience creating and using verification components and environments in a standard verification methodology, such as UVM.
• Experience with AI/compute IPs or multimedia IPs such as image processing or display.
• Experience with ASIC components, standard interfaces, performance verification, and memory system architecture.
• Experience with verification techniques, System Verilog Assertions (SVA) and assertion-based verification.
• Experience with GLS, low-power DV, and support of SOC DV.