Senior RTL Design Engineer, Digital Signal Processing

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As an RTL Design Engineer, you will be a key contributor to the physical implementation of next-generation TPU technology building ASICs for high-speed communication systems. You will take ownership of complex blocks, translating mathematical models into bit-exact silicon. Your expertise in front-end design flows will be vital in delivering the hardware that powers Google's advanced AI models and cloud services.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google.

Responsibilities

• Design and implement high-speed blocks, taking end-to-end ownership of complex modules within the larger system.
  
• Solve complex implementation issues related to GHz-frequency timing closure and advanced process nodes.
  
• Transform high-level architectural specifications and communication theory models into efficient, bit-exact implementations.
  
• Perform fixed-point analysis and micro-architectural trade-offs. Execute and optimize the front-end design flow for your assigned components to ensure, sign-off quality designs.
  
• Collaborate closely with verification teams to develop bit-exact C++/SystemC models and ensure seamless integration.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.
• 8 years of experience in digital signal processing (DSP) design or high-speed digital logic design.
• Experience implementing digital blocks for communication systems or PHY (Physical Layer) e.g., filters, interpolators, or timing recovery.
• Experience in MATLAB, Python, or C++

Preferred qualifications:

• Master's or PhD degree in Electrical Engineering, Computer Engineering, or a related technical field.
• Experience taking complex DSP designs through the full front-end flow: Synthesis (Design Compiler/Genus), STA (PrimeTime/Tempus), and CDC/LEC (Spyglass/Conformal).
  
• Experience with advanced FinFET process nodes (5nm, 3nm) and achieving timing closure at GHz frequencies.
  
• Experience with high-speed serial links (SerDes) and FEC (Forward Error Correction) implementation.
  
• Solid understanding of low-power design techniques and dynamic power optimization.