IC Packaging Engineer - WLP

Summary

Do you like to work on groundbreaking technology? Have a passion for creating amazing products? Our team is looking for a hardworking, IC Packaging Engineer with strong attention for details and love for excellence and precision to accomplish extraordinary results. In this highly impactful role, you will initiate package concepts, own and drive sophisticated package selection, new product package structure and configuration optimization. You will be responsible for packaging integration and package technology development for a variety of projects including SoC.

Description

You'll drive package integration across SoC and advanced 2.5D / 3D packaging projects, from architecture trade-off studies through characterization, modeling, and product delivery. You'll manage process development and enable MP-ready packaging solutions on product, own complex technical deliverables end-to-end, and lead DOEs and build execution with foundry and OSAT partners. You'll also serve as a technical anchor across design, test, reliability, and product teams. We're looking for a seasoned engineer with deep packaging expertise, strong cross-functional and supplier partnership skills, and a solution-oriented mindset grounded in engineering physics.

Responsibilities

• Lead packaging technology development, including advanced 2.5D / 3D packaging
• Own SoC package integration end-to-end, driving multi-functional teams across design, test, reliability, and product
• Drive package architecture and package integration innovation
• Partner with foundry and OSAT to bring packaging solutions from concept to HVM.
• Influence the industry through sophisticated package solutions, new material development, and spec definition
• 5% International travel

Minimum Qualifications

• BS and 10+ years of relevant industry experience or equivalent

Preferred Qualifications

• MS or PhD in a relevant discipline, with a thesis or coursework in semiconductor packaging, materials, thermal, mechanical, or electrical modeling
• Deep experience in the Semiconductor Packaging field, with a proven track record taking packages from concept to HVM
• Established expertise in Wafer Level Packaging, 2.5D packaging, and 3D packaging technology.
• Strong knowledge in materials characterization and analysis.
• Broad understanding of packaging technologies, assembly processes, IC packaging materials, reliability standards, and FA techniques.
• Proven experience with package design software (APD, Virtuoso, or equivalent).
• Demonstrated experience in memory packaging.
• Excellent interpersonal skills, with a track record of strong business partnerships and cross-functional collaboration, including overseas suppliers.
• Ability to work independently and orchestrate complex, multi-team projects with minimal supervision.
• Solution-oriented engineer with proven fundamentals in engineering physics.
• Strong program management skills.