CPU Design for Testing Engineer

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will be responsible for designing, developing, and deploying Design For Test (DFT) solutions to design our next generation advanced CPUs. As a member of a fast-paced multi-disciplinary team, you will use your creativity and varied range of engineering experience to explore solutions to a variety of engineering problems. Additionally, you will participate in the design, analysis, and prototyping of new concepts.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

• Partner strategically with RTL, architecture, Physical Design, Product Engineering (PDTE), Silicon Validation (SiVal), and Technology teams to architect, implement, and verify DFT solutions for next-generation CPU designs.
• Push the limits of industry-standard Electronic Design Automation (EDA) tools and pioneer custom DFT methodologies to accelerate turnaround times, boost productivity, and deliver test coverage.
• Develop, debug, and optimize high-quality production test patterns for Automatic Test Equipment (ATE) flows to ensure flawless silicon delivery.
• Act as a core pillar of the DFT group, mentoring peers and fostering a culture of seamless, high-impact collaboration across all engineering functions.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Science Engineering, or a related field, or equivalent practical experience.
  
• 8 years of experience in high-speed design, including implementation and Power Performance Area (PPA) optimization leveraging industry-standard toolsets.
• Experience in one or more sign-off convergence in areas like Static Timing Analysis (STA) electrical checks and physical verification domains.

Preferred qualifications:

• Experience applying AI/ML assisted DFT design techniques to drive next-generation scaling and faster physical design closure.
• Experience developing novel DFT solutions, silicon bring-up, and validation.
• Experience extracting design parameters, analyzing Quality of Results (QoR) metrics, and identifying performance trends, with proficiency in scripting (Python, Tcl, Perl) and data mining.
• Knowledge of high performance and low power design DFT techniques.
  
• Understanding of the end-to-end flows (e.g., design, verification, DFT, physical design implementation and static timing analysis).