Senior ASIC Verification Engineer

Hewlett Packard Enterprise•Apply•Published 3 days ago•First seen 1 days ago

Senior ASIC Verification EngineerThis role has been designed as 'Hybrid' with a requirement that you will work on average 2 days per week from an HPE office.

Who We Are:

Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world. Our culture thrives on finding new and better ways to accelerate what’s next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE.

Job Description:

Location: Durham, NC

This role has been designed as ‘Hybrid’ with an expectation that you will work on average 2 days per week from our Durham office. US Citizenship Preferred

Who We Are:

Job Family Definition:

You will architect, design, and implement complex networking ASICs. You will create chip‑level and block‑level architecture and micro‑architecture, write high‑quality RTL, and work closely with verification and physical design teams to deliver clean, efficient, and high‑performance silicon.

Responsibilities:

Define ASIC architecture for networking chips, including data paths, packet processing, control logic, memory structures, and interfaces.
Develop detailed micro‑architecture for complex blocks and ensure they meet functional and performance goals.
Write clear, efficient, synthesizable RTL (SystemVerilog/Verilog) for the designed blocks. Create assertions and assist in functional coverage
Work closely with verification engineers to ensure the RTL is fully tested, bug‑free, and meets all functional requirements.
Provide guidance to the verification team on test plans, coverage goals, corner cases, and expected behavior.
Collaborate with physical design engineers to ensure the design meets timing, area, and power targets.
Review synthesis, timing, and power reports, and update RTL or micro‑architecture as needed.
Participate in design reviews, provide clear feedback, and ensure compliance with design guidelines.
Support integration and debug during simulation, emulation and silicon bring‑up.
Identify technical risks early and propose simple, effective solutions.

Education and Experience Required:

Bachelor's, Master's or PHD degree in Electrical Engineering, Computer Science or Computer Engineering or equivalent.
Typically, 8+ years' experience

Knowledge and Skills:

Strong understanding of ASIC architecture and micro‑architecture.
Strong background in networking ASICs (switching, routing, packet processing, or similar preferred).
Expert in RTL coding in Verilog or SystemVerilog, assertions and functional coverage
Strong knowledge of digital design fundamentals, pipelining, clocking, resets, FIFOs, arbiters, and data path design.
Experience working with verification teams and understanding of UVM‑based flows.
Experience working with physical design teams and understanding constraints for timing, power, and area.
Familiarity with EDA tools for simulation, synthesis, lint, CDC, timing analysis, and power analysis.
Good written and verbal communication skills.
History of technical contributions, innovation, or mentorship.

What We Can Offer You:

Health & Wellbeing

We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing.

Personal & Professional Development

We also invest in your career because the better you are, the better we all are. We have specific programs catered to helping you reach any career goals you have — whether you want to become a knowledge expert in your field or apply your skills to another division.

Unconditional Inclusion

We are unconditionally inclusive in the way we work and celebrate individual uniqueness. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good.

Let's Stay Connected:

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Job:

Engineering

Job Level:

TCP_04"The expected salary/wage range for this position is provided below. Actual offer may vary from this range based upon geographic location, work experience, education/training, and/or skill level.
– United States of America: Annual Salary USD 135,000 - 310,500 in North Carolina
The listed salary range reflects base salary. Variable incentives may also be offered."

Information about employee benefits offered in the US can be found at https://myhperewards.com/main/new-hire-enrollment.html

HPE is an Equal Employment Opportunity/ Veterans/Disabled/LGBT employer. We do not discriminate on the basis of race, gender, or any other protected category, and all decisions we make are made on the basis of qualifications, merit, and business need. Our goal is to be one global team that is representative of our customers, in an inclusive environment where we can continue to innovate and grow together. Please click here: Equal Employment Opportunity.

Hewlett Packard Enterprise is EEO Protected Veteran/ Individual with Disabilities.

HPE will comply with all applicable laws related to employer use of arrest and conviction records, including laws requiring employers to consider for employment qualified applicants with criminal histories.

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