Senior Pre-Silicon Verification Engineer

Job Details:

Job Description: 

About Intel Central Engineering Group 

Intel's Central Engineering Group (CEG) is committed to transforming engineering processes while expanding market reach through internal product development and external ASIC design services. Three interconnected pillars drive CEG's mission to enhance Intel's engineering execution and market opportunities, all guided by a data-driven approach that ensures scalable impact. 

Position Overview 

We are seeking a Senior Mixed Signal Verification Engineer specializing in clock generator IP verification to ensure functional correctness of PLL/FLL designs. This role combines digital verification expertise with mixed-signal validation capabilities, requiring collaboration across architecture, RTL development, and analog design teams to deliver high-quality clock generation solutions. 

Key Responsibilities 

Clock Generator IP Verification 

• Perform comprehensive functional verification of clock generator IPs including PLL/FLL to ensure designs meet specification requirements 
• Proactively and independently develop test benches, verification environments, tests, and checkers/assertions ensuring coverage compliance with IP microarchitecture specifications 
• Lead Mixed Signal Validation (MSV) activities by running AMS simulations and collaborating cross-functionally to identify, root-cause, and resolve schematic bugs 

Verification Environment Development & Debug 

• Replicate, root cause, and debug complex issues in the pre-silicon environment using systematic debugging methodology 
• Maintain and improve existing functional verification infrastructure and methodology for multiple generations of IP test benches 
• Document comprehensive test plans and drive technical reviews with design teams 

Cross-Functional Collaboration & Development 

• Collaborate with architects, RTL developers, and analog schematic owners to improve verification of architectural and microarchitectural features 
• Participate actively in the definition of architecture and microarchitecture features of the IP being designed 
• Participate in RTL development activities and contribute to design optimization 

Specialized Knowledge 

• Understanding of mixed-signal design principles and AMS simulation techniques 
• Knowledge of clock generation architectures and timing analysis 
• Familiarity with analog verification methodologies and tools 
• Experience with clock domain crossing verification and analysis 

Core Competencies 

• Strong analytical and problem-solving skills for complex verification challenges 
• Ability to work independently while collaborating effectively across multiple teams 
• Excellent documentation and communication skills for technical reviews 

Qualifications:

The Minimum qualifications are required to be considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. 

Minimum Qualifications 

• Bachelor's degree in Electronics/Electrical/Computer Engineering 
• 3+ years of experience in Design Verification and Validation methodologies with UVM, SystemVerilog, and industry-standard EDA tools  
• 3+ years of experience in scripting languages such as Python and Perl 

Preferred Qualifications 

• Post graduate degree in Electronics/Electrical/Computer Engineering 
• Experience with debug methodologies  
• Experience with RTL development and design implementation 
• Experience working on PLL/FLL or SoC clocking architectures and verification 

What We Offer 

• Opportunity to work on cutting-edge clock generation technologies and mixed-signal verification 
• Collaboration with world-class engineers in architecture, design, and verification 
• Access to advanced EDA tools and verification infrastructure 
• Professional development in mixed-signal verification and clock design 
• Direct impact on Intel's IP portfolio and engineering execution excellence

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location: 

US, Oregon, Hillsboro

Additional Locations:

US, Arizona, Phoenix, US, California, Santa Clara, US, Massachusetts, Beaver Brook, US, Texas, Austin

Business group:

The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $141,910.00-232,190.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.