Senior Physical Design Floorplan Engineer, Google Cloud

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities

• Define and drive to the implementation of physical design SoC Floorplan methodologies.
• Take ownership of Floorplanning of one or more top level.
• Drive to the closure of Floorplanning of Subsystem (SS) or top level.
• Contribute to design methodology, libraries, and code review.
• Define the physical push down methodologies for the physical design engineers.

Minimum qualifications:

• Bachelor’s degree in Electrical Engineering or equivalent practical experience.
• 8 years of experience with advanced design, including clock or voltage domain crossing, Design for Testing (DFT), and low power designs.
• Experience with System on a Chip (SoC) cycles.
• Experience in high-performance, high-frequency, and low-power designs.

Preferred qualifications:

• Experience in VLSI design in SoC or multiple-cycles of SoC in ASIC design.
• Experience in automations and scripting with TCL/Python.
• Experience with Floorplan convergence on Sub-System (SS) or SoC.