Silicon Physical Verification Engineer, Google Cloud

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As a Physical Design Verification Engineer, you will collaborate with physical design, circuits, technology, and package leads and drive the overall sign-off physical convergence for high-performance designs. You will also define the overall physical convergence methodology, plan out the timelines, and work closely with the block owners to achieve physical convergence through systematic fixes and minimal manual effort.

In this role, you will perform technical evaluations of Electronic Design Automation (EDA) tools, process nodes, and IPs and provide recommendations. You will participate in the development of exceptional technology in high-performance computing.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities

• Own and perform physical verification steps including Design Rule Check (DRC), Layout Versus Schematic (LVS), (Electrical Rule Check (ERC), (Design for Manufacturing (DFM) at the block, subsystem, and full chip level.
• Own and define process flow and methodology for full chip assembly and tapeout signoff.
• Work with floorplan and physical design engineers to drive physical verification convergence.
• Perform technical physical evaluations of vendors, process nodes, and Intellectual Property (IP).
• Contribute to design methodologies and automation scripts for physical verification steps.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, a related field, or equivalent practical experience.
  
• 5 years of experience in ASIC physical design flows with emphasis on physical verification convergence and tapeout signoff.
• Experience in ASIC physical design, physical design verification, and various methodologies.
  
• Experience in physical verification tools, Python, Tcl, or Perl scripting.
  

Preferred qualifications:

• Master's degree in Electrical Engineering, or a related field.
  
• Experience in Padrings, Bumps, Redistribution Layer (RDL), and IP integration (e.g., memories, IOs, and analog IPs).
  
• Experience in Place and Route (PnR) tools like Fusion Compiler or Innovus with physical convergence.
• Knowledge of semiconductor device physics and translator characteristics.