Senior Design Technology Co-Optimization Engineer

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As a Design Technology Co-Optimization (DTCO) Engineer, you will bridge the gap between process technology and product architecture to define the next generation of datacenter-class silicon. You will be responsible for extracting maximum process entitlement by evaluating advanced logic nodes and emerging transistor architectures.

In this role, you will conduct Place and Route (P&R) experiments and sensitivity analyses to influence standard cell library architecture, metal stack definitions, and design rules. You will collaborate with Foundry, IP, and Architecture teams to identify Power Purchase Agreement (PPA) bottlenecks and drive System Technology Co-Optimization (STCO) initiatives.

Your work will involve performing high-fidelity physical implementation sweeps, analyzing the impact of scaling boosters, and developing automated methodologies to quantify PPA gains. By navigating the trade-offs between process complexity and design performance, you will ensure Google’s hardware achieves efficiency and power density.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

The US base salary range for this full-time position is $156,000-$229,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Execute high-fidelity Place and Route (P&R) experiments to evaluate the PPA impact of advanced process features, library architectures, and design rule variations on datacenter-class IP.
  
• Drive Design Technology Co-Optimization by collaborating with foundries and internal technology teams to define optimal metal stacks, track heights, and scaling boosters (e.g., backside power delivery, buried power rails).
  
• Quantify process entitlement through systematic benchmarking of logic and memory macros, identifying bottlenecks in power density and timing closure for next-generation nodes.
  
• Develop automated physical design methodologies and flows to accelerate technology pathfinding and enable rapid what-if analysis of emerging transistor architectures.
  
• Influence System Technology Co-Optimization (STCO) by partnering with Hardware Architects and Circuit Designers to translate process-level innovations into system-level performance gains.
  

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
• 5 years of experience in Physical Design (RTL-to-GDS) or Technology Development, focusing on advanced nodes (e.g., 7nm, 5nm, or below).
• Experience with industry-standard Place and Route (P&R) tools and Static Timing Analysis (STA) tools.

• Experience in scripting and automation using Tcl and Python (or Perl) to manage design sweeps and data extraction.

• Experience in CMOS device physics, FinFET/nanosheet architectures, and the impact of layout parasitics on PPA.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  
• 10 years of experience in Design Technology Co-Optimization, including standard cell library characterization, metal stack optimization, and evaluation of scaling boosters (e.g., backside power delivery).
• Experience working with major foundry technology files (PDKs) and interpreting Design Rule Manuals (DRM) to guide physical implementation.
• Experience with Register Transfer Level (RTL) synthesis and standard cell library optimization.
• Expertise in power integrity and reliability analysis and physical verification.
• Familiarity with datacenter-class IP blocks (e.g., high-performance CPU/GPU cores, SRAM arrays, or high-speed interconnects).