Senior DFT Engineer

Intel•Apply•Published 1 days ago•First seen 2 hours ago

Job Details:

Job Description:

Are you passionate about computer graphics and disrupting the industry with your innovation and working with leading Engineers on Intel's latest GPU/CPU architecture? Do you love collaborating with diverse teams to help achieve Best-In-Class visual experiences that enable users to immerse themselves in a new visual future? Then AI SOC Engineering team has opportunities for you. Our Hardware development team designs and validates the future of GPU Cores.

We are looking for Senior DFT Design Engineer to join our team who are ready to make significant impacts in graphics and visual computing. As a member of the AI SOC Engineering group, you will be responsible for one or more of the following activities:

You will work on the design, RTL/GLS validation, automation, and/or timing analysis for Scan/ATPG and/or DFT/JTAG controller
You will also contribute or be involved with trace/pattern generation efforts as well as post-silicon enabling, debug support, and/or analysis of the DFx features/content types you are responsible for.
Develops the logic design, register transfer level (RTL) coding, and simulation for graphics IPs (including graphics, compute, display, and media) required to generate cell libraries, functional units, and the GPU IP block for integration in full chip designs.
Participates in the definition of architecture and microarchitecture features of the block being designed.
Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
Reviews the verification plan and implementation to ensure design features are verified correctly across verification hierarchies, drives unit level verification, and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
Supports SoC customers to ensure high-quality integration of the GPU block.

The ideal candidate will exhibit the following traits/skills:

Excellent written and verbal communication skills
Demonstrate Leadership ability in driving execution
Demonstrate teamwork, problem solving and influencing skills
Ability to work with different geographical locations

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:
Bachelors Degree in Electrical Engineering, Computer Engineering, or related STEM degree and 5+ years of industry experience
OR Masters in Electrical Engineering, Computer Engineering or related STEM degree and 3+ years of industry experience
OR PhD in Electrical Engineering, Computer Engineering or related STEM degree and 2+ years of industry experience

Your experience should be in following

At least one of the key DFT features such as TAP/JTAG, Scan/ATPG or Array DFT (MBIST/PBIST) (This is a key skill requirement.)
SoC or IP DFT design, integration or verification
EDA tools such as ATPG tools, Siemens Tessent shell, VCS simulation and/or debug tools.

Preferred Qualifications:

Silicon enabling debug or test pattern development experience
Design automation skills and proficiency in programming or scripting languages
Structural design flows, including timing, routing, placement or clocking analysis
High volume manufacturing requirements and test flows
3D, media and display graphics pipelines
SoC architecture

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location:

US, California, Folsom

Additional Locations:

US, Arizona, Phoenix, US, California, Santa Clara, US, Oregon, Hillsboro

Business group:

At the Data Center Group (DCG), we're committed to delivering exceptional products and delighting our customers. We offer both broad-market Xeon-based solutions and custom x86-based products, ensuring tailored innovation for diverse needs across general-purpose compute, web services, HPC, and AI-accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership. Join us as we transform the data center segment through workload driven leadership products and close collaboration with our partners.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $141,910.00-200,340.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.