Senior CPU Formal Verification Engineer, Silicon

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

The US base salary range for this full-time position is $156,000-$229,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Plan the formal verification strategy, create the properties and constraints for various units of a Central Processing Unit (CPU) design.
• Solve problems from assertion properties to data-path vs model proofs to formal signoff of units.
• Architect and implement reusable formal verification components.
• Contribute improvements to methodologies to enhance formal verification results.
• Enable broad use of formal techniques by the full CPU team via mentoring and education.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience verifying digital logic at RTL using SystemVerilog for ASICs.
• Experience capturing design specification in a temporal assertion language (e.g., SVA or PSL).
• Experience with one or more Design Verification industry formal verification tools (e.g., JasperGold, VC Formal, Questa Formal, 360-DV, etc.).

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience with application of formal techniques on processor designs or cache coherency designs.
• Understanding of model checking, formal verification algorithms, and formal signoff.