Chip Packaging Technologist

Google•Apply•Published 3 days ago•First seen 3 days ago

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a Chip Packaging Technologist on the silicon integration team, your role is to develop advanced packaging solutions (2.5D/3D/3.5D) and packaging technologies for Machine Learning (ML) chips. This involves collaborating with product architects, SI/PI, Thermal/Mechanical, Assembly, and PCB engineers to create complex, high-performance packages. The goal is to optimize package substrate technologies for electrical performance, reliability, and assembly.You will be instrumental in identifying and incorporating advanced chip packaging technologies into the Google chip product design. As a Hardware Engineer for ASIC, you are central to developing and building the systems that form the core of the world's largest and most powerful computing infrastructure.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities

Manage the definition and execution of various test vehicles (eTV, tTV, mTV).
Proactively identify packing risks and document technical risk assessment for the test vehicle definition.
Work with foundries and OSATs to develop and execute engineering plans and test vehicles.
Define and implement DFx (DFM, DFR, DFT) methodologies for advanced packages.
Drive collaboration with multi-functional internal teams, OSATs and material suppliers to deliver chip package solutions.

Minimum qualifications:

Bachelor's degree in Materials, Mechanical, Electrical Engineering, a related field, or equivalent practical experience.
5 years of experience working with 3D packaging.
5 years of experience in working with foundries and OSATs for package development.

Preferred qualifications:

Experience in developing new technologies and driving innovations.
Experience in managing assembly houses or wafer foundries.
Understanding of multidisciplinary interactions between packaging technology, chip package electrical design, thermal and mechanical performance, and manufacturability/reliability.
Knowledge of 2.5D and 3D packaging technologies, and advanced substrate technologies for HPC applications.
Knowledge with general package assembly process, packaging materials, and reliability requirements (component and board level).