Chip Packaging Technologist, Google Cloud

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will work on package development of chip package technologies. You will be directing all technical aspects of package design, assembly process, package materials and reliability tests. You will perform early feasibility studies using test vehicles, creation of specifications and provide guidance for thermal, mechanical, electrical and package substrate design. You will be leading package design reviews, solving all technical issues associated with package reliability, process, thermal, and electrical issues. You will also work with multi-functional cross teams from different organizations and various vendors to incorporate their inputs into package development and successfully roll out for production.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities

• Develop and qualify substrate solutions for Google Tensor Processing Units (TPUs). Identify and mitigate packaging risks.
• Drive advanced packaging solutions from concept to production including manufacturing, electrical, thermal, and mechanical requirements.
• Establish package development engineering plans and conduct experiments using mechanical/thermal test vehicles to plan package materials. Generate assembly process and reliability test plans.
• Drive collaboration with multi-functional internal teams, Outsourced Assembly and Tests (OSATs) and material suppliers to deliver chip package solutions for production.
• Drive foundry technologies to package interactions. Define and implement Design for Excellence (Design for Manufacturability (DFM), Design for Reliability (DFR), Design for Testing (DFT)) methodologies for advanced packages.

Minimum qualifications:

• Bachelor's degree in Materials, Mechanical, Electrical Engineering, a related field, or equivalent practical experience.
• 5 years of experience in working with 3D packaging.
• 5 years of experience in working with foundries and OSATs for package development.

Preferred qualifications:

• Experience in semiconductor package manufacturing, with yield optimization and new product introduction.
• Experience in developing new technologies.
• Experience with general package assembly process, packaging materials, and reliability requirements.
• Experience in managing assembly houses or wafer foundries.
• Knowledge of 2.5D and 3D packaging technologies, and advanced technologies for High Performance Computing (HPC) applications.
• Knowledge of multidisciplinary interactions between packaging technology, chip package electrical design, thermal and mechanical performance, and manufacturability/reliability.