Signal and Power Integrity Engineer, Cloud

Be part of the team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a Signal and Power Integrity Engineer you will be responsible for the chip package design with signal/power integrity simulation and characterization in the chip, package and system level.

You will be the part of a team with Chip Architects, ASIC Engineers, Physical Design and other Signal Integrity (SI)/Power Integrity (PI) Engineers. You will work with various cross-functional teams, including Chip Design, System Design, software team and vendors. You will drive chip packaging signal and power implementations from product planning to New Product Introduction (NPI).

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities

• Co-design by performing SI/PI analysis to involve in the product definition and improve chip floor plan, power tree structure, net lists, etc for High Performance Computing (HPC) based on 2.5D/3D package technology.
• Conduct post silicon validation and qualification of high speed interface for New Product Introduction (NPI).
• Develop Methodologies to enhance simulation accuracy and productivity.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 2 years of experience in the Signal Integrity (SI)/Power Integrity (PI) field.
• Experience in industry SI/PI modeling tool chains (e.g., HFSS, ADS, Sigrity, or Siwave, etc).

Preferred qualifications:

• Experience in post silicon correlation with models.
• Experience with 2.5D/3D package design such as silicon interposer, silicon bridge, 3D die stacking.
• Experience in cross-functional collaboration with chip top design, physical design, STA, package, system design, and validation teams.
• Experience in programming and data analysis with Matlab, Python, C++ and statistical tools to establish automation flows and data processing.
• Knowledge of memory testing, next generation memory, chiplet standards and timing budget methodology.
• Understanding of on and off chip power delivery and Static timing analysis (STA)/voltage budget.