Physical Design and Implementation Engineer, ASIC

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

• Develop high-performance hardware and software to enable Google’s continuous innovations in working with Application Specific Integrated Circuits (ASIC) as a Physical Design and Implementation Engineer.
• Collaborate with Architects and Logic Designers to initiate architectural feasibility studies, establish timing, power, and area design objectives, and investigate Register Transfer Language (RTL)/design trade-offs for physical design closure.
• Work with Verification and Software teams to comprehend and execute the design requirements for clocking and power management.
• Develop all aspects of ASIC RTL2GDS implementation for high Performance, Power, Area (PPA) designs.
• Manage block and sub-system level physical implementation and Quality of Results (QoR) (e.g., power, timing, area).

Minimum qualifications:

• Bachelor's degree in Mechanical Engineering, Electrical Engineering, Industrial Engineering or equivalent practical experience
• 5 years of experience in ASIC physical design flows and methodologies in advanced process nodes.
  
• Experience in synthesis, PnR and sign-off optimizations, sign-off convergence, including Static Timing Analysis (STA), electrical checks and physical verification.
• Experience in one or more of synthesis/PnR tools (e.g., Genus, Innovus, DC and ICC, STA tools).

Preferred qualifications:

• Bachelor's or Master's degree in Computer Science, or a related technical field.
• 3 years of experience in ASIC physical design flows with strong emphasis on physical verification convergence and tapeout signoff.
• Experience in engineering across physical design and top-level implementation.