Senior CPU RTL Design Engineer, Silicon

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

The US base salary range for this full-time position is $156,000-$229,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Contribute to CPU subsystem design, focusing on SoC integration related activities, functional debug and preparation for post-silicon testing.
• Participate in post-silicon CPU subsystem design activities for mobile devices (phone-class SoCs), focusing on hardware-software integration and validation of CPU features in real silicon.
• Contribute to CPU subsystem microarchitecture and RTL design, delivering production-quality designs that meet Power, Performance, and Area (PPA) goals for next-generation processors.
• Develop expertise in cache subsystems or vector arithmetic dataflow design and debug.
• Propose and implement performance-enhancing microarchitecture features with efficiency in mind, working closely with architects and performance teams to facilitate decision-making.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
• 8 years of experience with of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
• Experience with silicon validation and hardware debugging, specifically for phone/mobile-class application processors.
• Experience with logic optimization techniques and RTL static checks (e.g., CDC, LINT).

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  
• Excellent background and an understanding of Advanced Reduced Instruction Set Computing (RISC) Machine (ARM) architecture, in particular, around debug features.
• Excellent background and an understanding of the Advanced Microcontroller Bus Architecture (AMBA) Coherent Hub Interface (CHI) protocol and system-level coherency management.