Asic Engineer, Implementation

Description

Meta Platforms, Inc. (Meta), formerly known as Facebook Inc., builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps and services like Messenger, Instagram, and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. To apply, click “Apply to Job” online on this web page.

Responsibilities

Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power. Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them. Perform Power Estimation at RTL and Gate Level and identify power reduction opportunities. Run Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic Equivalency failures. Perform RTL Lint and work with the Designers to create waivers. Perform RTL Clock Domain Crossing Analysis and do block level CDC signoff. Perform RTL Reset Domain Crossing Analysis and do block level RDC signoff. Perform RTL DFT Analysis and improve the DFT coverage for Stuck-at faults. Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top-level including SOC. Analyze the inter-block timing and come up with IO budgets for the various partition blocks. Developing Automation scripts and Methodology for all FE-tools including (Lint, CDC, RDC, Synthesis, STA, Power). Work closely with the Design Engineers, DV Engineers, Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback.

Qualifications

Bachelor's degree (or foreign degree equivalent) in Electronics Engineering, Computer Engineering, Computer Science, Analytics, or related field and 3 years of work experience in the job offered or related occupation Requires 3 years of experience in the following skills: Front End Design Integration RTL design using Verilog RTL Physical Synthesis and design optimization for Power, Performance, Area Knowledge of front-end and back-end ASIC tools Floor planning for I/O, Hard Macros Writing Timing Constraints for Block Synthesis, Timing Using Synthesis Tools (Design Compiler, Genus) Using Physical Design Tools ( Innovus, ICC) Using Static Timing Tools (Primetime) Managing multiple design releases and working with cross functional teams to support and debug timing, area, power issues and Communicating across functional internal teams and vendors

Compensation: $166,000/year to $198,220/year + bonus + equity + benefits