CMOS Test Silicon Engineer, Raxium

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's Raxium display group has established a revolutionary semiconductor materials display technology that enables new functionality in display products, bringing to users a closer and more natural linkage between the digital and physical realms in applications such as augmented reality (AR) and light-field display. With start-up roots and a state-of-the-art compound semiconductor fab in Silicon Valley, Raxium is seeking to build upon its engineering team with an aim to disrupt next-generation display markets.

Responsibilities

• Plan daily test activities and manage operations, including technical directions for test technicians and operators for our partners in Taiwan.
• Collaborate with test program design houses to maintain, enhance, and optimize existing test programs and functional sequences.
• Establish relationships with a new test analysis software/service company to meticulously catalog and manage all ongoing test activities, results, maps, and related data.
• Assist in the root-cause analysis of complex silicon failures, collaborating closely with Design and Test Engineering teams.
• Advocate enhancements in the validation flow, including the implementation of new tools, methodologies, and scripts to significantly boost test efficiency and coverage.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
• 5 years of experience in ASIC/SoC design, with a focus on test, and custom chip development with Design for Test (DFT) implementation.
• Experience working with vendors and managing development schedule and specifications.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  
• Experience with EDA tools for synthesis, Static Timing Analysis (STA), DFT, and test tool conversion.
• Experience with DFT techniques such as hierarchical DFT, compression, and diagnosis.
• Experience in hardware description languages (e.g., Verilog, SystemVerilog).
• Experience in display back plane panel technology.
• Excellent problem-solving and communication skills.