Senior ASIC RTL Engineer, Integration

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.

Responsibilities

• Work with a team of RTL engineers with IP/Subsystem development, plan tasks, build subsystems, run quality flows, create automation, hold code and design reviews, code development of complex features in the IP/Subsystem.
• Interact closely with the architecture team and develop implementation (microarchitecture and coding) strategies to meet quality, schedule and PPA for the IP.
• Work closely with the cross-functional team of Verification, Design for Test, Physical Design and Software teams to make design decisions and represent project status throughout the development process.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog.
• Experience with automation scripting languages like Perl, Python, TCL etc.
• Experience with logic synthesis techniques to optimize area, performance and power, as well as low-power design techniques.
• Experience in integrating, designing and automating flows of sub-systems, interconnects (AXI 4/5, ACE-Lite, AHB, APB) and other component IP's.

Preferred qualifications:

• Master's or PhD degree in Electrical Engineering, Computer Engineering or Computer Science.
• 12 years of experience with digital logic design principles, basic RTL design concepts, and languages, such as Verilog or SystemVerilog.
• Experience with ASIC or FPGA design verification, synthesis, timing/power analysis, and DFT.
• Knowledge of high-performance and low-power design techniques, assertion-based formal verification, FPGA and emulation platforms, and SOC architecture.
• Knowledge of memory compression, fabric, coherence, cache, or DRAM.