Formal Verification Engineer, Platform, IP, CompIP

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

• Plan the formal verification strategy, create the properties and constraints for complex digital design blocks.
• Lead a team of formal verification specialists while maintaining ownership of sign-off for critical, high-complexity modules.
• Utilized state-of-the-art formal tools to prove complex properties and achieve formal closure on massive state-space designs.
• Contribute improvements to methodologies to enhance formal verification results.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
• 8 years of experience with formal verification in SystemVerilog and SystemVerilog Assertion.
• Experience leading formal verification for IPs/sub-systems.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience in Formal Property Verification (FPV), with a proven track record of developing comprehensive property suites for high-complexity designs.
• Experience in low-power design verification.