Staff Silicon Design Verification Methodology Architect

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

• Work cross-functionally to debug failures and verify the functional correctness of the design.
  
• Lead the design and implementation of a scalable, high-performance SoC-level verification framework tailored for simulation acceleration.
• Architect and develop infrastructure that supports multi-language stimulus, specifically integrating C-testbench execution with SV/UVM agents and checkers.
• Implement advanced techniques to maximize simulation throughput, such as thread-based mechanisms or dynamic testbench splitting, aiming for significant performance gains.
• Develop and integrate transactors, hardware-compliant VIPs, and reusable infrastructure components that transition smoothly between simulation and emulation.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
• 10 years of experience in Design Verification and Emulation, and in leading SoC-level projects from planning to closure.
• Experience in Application-Specific Integrated Circuit (ASIC) development with System Verilog and Universal Verification Methodology.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  
• Experience with digital system based on AMBA Bus protocols like ACE/AXI/AHB/APB or similar complexity bus protocols.
• Experience in simulation acceleration using transactors, or vendor provided accelerated verification IP.
• Experience in performance analysis/debug techniques and in a lab environment working on ASIC bringup and test development.
• Ability to build emulation environments with one or more industry standard platforms like Zebu, HAPS, Palladium, Virtualizer, GEM5.