Senior Silicon Bring Up and Test Manager, Raxium

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's Raxium display group has established a revolutionary semiconductor materials display technology that enables new functionality in display products, bringing to users a closer and more natural linkage between the digital and physical realms in applications such as augmented reality (AR) and light-field display. With start-up roots and a compound semiconductor fab in Silicon Valley, Raxium is seeking to build upon its engineering team with an aim to disrupt next-generation display markets.

Responsibilities

• Plan daily activities and provide technical direction for test operations in Taiwan. Partner with design houses to maintain and improve test programs and functional sequences.
• Manage relationships with software vendors to catalog test results, maps, and related data.
• Drive validation flow improvements using new tools and scripts to improve test efficiency and coverage.
• Collaborate with the documentation team to validate specifications, margins, and acceptance criteria.
• Work with verification teams on test plans and logic debugging. Assist in root-cause analysis of silicon failures with design and test engineering teams.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 8 years of experience in ASIC or SoC design, including test, and custom chip development with Design-for-Test (DFT) implementation.
• Experience working with vendors and managing development schedule and specifications.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience with EDA tools for synthesis, Static Timing Analysis (STA), DFT, and test tool conversion.
• Experience with DFT techniques such as hierarchical DFT, compression, and diagnosis.
• Experience in display back plane panel technology.
• Experience in hardware description languages (e.g., Verilog, SystemVerilog).
• Excellent problem-solving and communication skills.