Silicon TPU Hardware Performance Architect, Google Cloud

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will be part of a team developing Artificial Intelligence (AI) accelerators for data centers, focusing on project definition, design, and implementation. You will participate in the design, architecture, documentation, and implementation of next-generation data center accelerators. Proficiency in performance modeling of the SOC, particularly fabrics/noc/Interconnects, is essential.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities

• Evaluate various silicon solutions for Google’s data center AI accelerator roadmap, including components, vendor co-developments, custom designs, and chiplets.
• Assess quantitatively fabrics across the entire life-cycle (e.g., early-architecture to post-silicon), and focus on performance and methods to detect deadlocks/livelocks.
• Lead the development of performance methodology, infrastructure, and simulation models.
• Contribute synthetic workload (WL) performance requirements by consulting WL experts on characteristics like latencies, bandwidth, and flow priorities.
• Support downstream silicon teams, including silicon validation and post-silicon groups.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering or equivalent practical experience.
• 8 years of experience in C++/SystemC TLM modeling or in a similar simulation process.
• Experience with specific SoC sub-systems: cache, memory, fabric, and network traffic topologies.
• Experience in performance modeling and analysis for SoCs, considering latency, bandwidth, and power expectations and setting up and integrating performance/functional simulators, analysis, or workloads.
• Experience with scripting or in RTL validation environments.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering or equivalent practical experience.
• Experience collaborating with software teams to optimize the hardware/software interface.
• Experience in performance analysis and modeling, including defining and executing performance test plans.
• Experience in programming languages like C++ and Python, and in developing large simulation projects.
• Experience using Machine Learning (ML) tools for smarter solutions.
• Understanding of key architectural concepts: bus architectures, accelerators, memory hierarchies, On die fabrics, AMBA specifications, and high-performance, low-power design techniques.